TOP=TOP_0, SRTC_ENV=SRTC_ENV_0, LPCALB_EN=LPCALB_EN_0, SRTC_INV_EN=SRTC_INV_EN_0, LPTA_EN=LPTA_EN_0, LPCALB_VAL=LPCALB_VAL_0, MC_ENV=MC_ENV_0, DP_EN=DP_EN_0
SNVS_LP Control Register
| SRTC_ENV | Secure Real Time Counter Enabled and Valid When set, the SRTC becomes operational 0 (SRTC_ENV_0): SRTC is disabled or invalid. 1 (SRTC_ENV_1): SRTC is enabled and valid. |
| LPTA_EN | LP Time Alarm Enable When set, the SNVS functional interrupt is asserted if the LP Time Alarm Register is equal to the 32 MSBs of the secure real time counter 0 (LPTA_EN_0): LP time alarm interrupt is disabled. 1 (LPTA_EN_1): LP time alarm interrupt is enabled. |
| MC_ENV | Monotonic Counter Enabled and Valid When set, the MC can be incremented (by write transaction to the LPSMCMR or LPSMCLR) 0 (MC_ENV_0): MC is disabled or invalid. 1 (MC_ENV_1): MC is enabled and valid. |
| LPWUI_EN | LP Wake-Up Interrupt Enable This interrupt line should be connected to the external pin and is intended to inform the external chip about an SNVS_LP event (tamper event, MC rollover, SRTC rollover, or time alarm ) |
| SRTC_INV_EN | If this bit is 1, in the case of a security violation the SRTC stops counting and the SRTC is invalidated (SRTC_ENV bit is cleared) 0 (SRTC_INV_EN_0): SRTC stays valid in the case of security violation. 1 (SRTC_INV_EN_1): SRTC is invalidated in the case of security violation. |
| DP_EN | Dumb PMIC Enabled When set, software can control the system power 0 (DP_EN_0): Smart PMIC enabled. 1 (DP_EN_1): Dumb PMIC enabled. |
| TOP | Turn off System Power Asserting this bit causes a signal to be sent to the Power Management IC to turn off the system power 0 (TOP_0): Leave system power on. 1 (TOP_1): Turn off system power. |
| PWR_GLITCH_EN | Power Glitch Enable By default the detection of a power glitch does not cause the pmic_en_b signal to be asserted |
| LPCALB_EN | LP Calibration Enable When set, enables the SRTC calibration mechanism 0 (LPCALB_EN_0): SRTC Time calibration is disabled. 1 (LPCALB_EN_1): SRTC Time calibration is enabled. |
| LPCALB_VAL | LP Calibration Value Defines signed calibration value for SRTC 0 (LPCALB_VAL_0): +0 counts per each 32768 ticks of the counter clock 1 (LPCALB_VAL_1): +1 counts per each 32768 ticks of the counter clock 2 (LPCALB_VAL_2): +2 counts per each 32768 ticks of the counter clock 15 (LPCALB_VAL_15): +15 counts per each 32768 ticks of the counter clock 16 (LPCALB_VAL_16): -16 counts per each 32768 ticks of the counter clock 17 (LPCALB_VAL_17): -15 counts per each 32768 ticks of the counter clock 30 (LPCALB_VAL_30): -2 counts per each 32768 ticks of the counter clock 31 (LPCALB_VAL_31): -1 counts per each 32768 ticks of the counter clock |
| BTN_PRESS_TIME | This field configures the button press time out values for the PMIC Logic |
| DEBOUNCE | This field configures the amount of debounce time for the BTN input signal |
| ON_TIME | The ON_TIME field is used to configure the period of time after BTN is asserted before pmic_en_b is asserted to turn on the SoC power |
| PK_EN | PMIC On Request Enable The value written to PK_EN will be asserted on output signal snvs_lp_pk_en |
| PK_OVERRIDE | PMIC On Request Override The value written to PK_OVERRIDE will be asserted on output signal snvs_lp_pk_override |
| GPR_Z_DIS | General Purpose Registers Zeroization Disable |